Documentation on the MC68030 processor by Bjrn Ove rthun Also known as Zynx/Inferiors (ex Imagina). or as Hei on irc I wrote this doc as there are no good docs on the 030. This doc will be ugraded a couple of times - at least every month. The next version will include about 10 more pages about optimizing any ideas or suggestions contact: Bjorn Ove Arthun, ulsbergtunet 11, 4033 Forus, Norway I am a game developer. Check out my stargate 2000 game for the Falcon on this web page: http://www-users.informatik.rwth-aachen.de/~neil/ad/ ---------------------------------------------------------------------------- +--------------------------------------------------------------------------+ |Mnemonic |Description |Mnemonic |Description | +--------------------------------------------------------------------------+ |ACBD |Add Decimal with Extend |MULS |Signed Multiply |ADD |Add |MULU |Unsigned Multiply |ADDA |Add Address |---------|--------------------------- |ADDI |Add Immediate |NBCD |Negate Decimal with Extend |ADDQ |Add Quick |NEG |Negate |ADDX |Add with Extend |NEGX |Negate with Extend |AND |Logical AND |NOP |No Operation |ANDI |Logical AND Immediate |NOT |Logical Complement |ASL, ASR |Arithmetic Shift L/R |---------|--------------------------- |-----------| |OR |Logical inclusive Or |Bcc |Branch Conditionally |ORI |Logical inclusive Immediate |BCHG |Test Bit and change |---------|--------------------------- |BFCLR |Test Bit Field and Clr |PACK |Pack BCD |BFEXTS |Signed Bit Field Extract |PEA |Push Effective Address |BFEXTU |Unsigned -----||----- |---------|--------------------------- |BFFFO |Bit Field Find First One |RESET |Reset External Devices |BFINS |Bit Field Insert |ROL, ROR |Rotate Left and Right |BFSET |Test Bit Field and Set |ROXL,ROXR|Rotate with Extend |BFTST |Test Bit Field |RTD |Return and Deallocate |BKPT |Breakpoint |RTE |Return from Exception |BRA |Branch |RTM |Return from Module |BSET |Test Bit and Set |RTR |Return from Restore Codes |BSR |Branch to Subroutine |RTS |Return from Subroutine |BTST |Test Bit |---------|--------------------------- |-----------| |SBCD |Subtr. Decimal with Extend |CALLM |Call Module |Scc |Set Conditionally |CAS |Compare and Swap Operands|STOP |Stop |CAS2 |As above in Dual Mode |SUB |Subtract |CHK |Check Reg: Against Bound |SUBA |Subtract Address |CHK2 |Check Against Upper and |SUBI |Subtract Immediate | |Lower Bounds |SUBQ |Subtract Quick |CLR |Clear |SUBX |Subtract with Extend |CMP |Compare |SWAP |Swap Register words |CMPA |Compare Address |---------|--------------------------- |CMPI |Compare Immediate |TAS |Test Operand and Set |CMPM |Compare Memory to Memory |TRAP |Trap |CMP2 |Compare Register Against |TRAPcc |Trap Conditionally | |Upper and Lower Bounds |TRAPV |Trap on Overflow |-----------| |TST |Test Operand |DBcc |Test Condition, Decrement|---------|--------------------------- | |and Branch |UNLK |Unlink |DIVS, DIVSL|Signed Divide |UNPK |Unpack |DIVU, DIVUL|Unsigned Divide |------------------------------------- |-----------| | CoProcessor Instructions |EOR |Exclusive Or |------------------------------------- |EORI |Exclusive Or Immediate |cpBcc |Branch Conditionally |EXG |Exchange Registers |cpDBcc |Test Condition, |EXT, EXTB |Signed Extend | |Decrement and Branch |-----------| |cpGEN |Coprocessor General Instr. |ILLEGAL |Take Illegal Instruction |cpRESTORE|Restore Internal State | |Trap |cpSAVE |Save Internal State |-----------| |cpScc |Set Conditionally |JMP |Jump |cpTRAPcc |Trap Conditionally |JSR |Jump to Subroutine |---------+--------------------------- |-----------| | Unofficial Instructions |LEA |Load Effective Address |------------------------------------- |LINK |Link and Allocate | | |LSL, LSR |Logical Shift Left and | |Not complete. :) | |Right | | |-----------| | | |MOVE |Move | | |MOVEA |Move Address | | |MOVE CCR |Move Condition Code Reg. | | |MOVE SR |Move Status Register | | |MOVE USP |Move User Stack Pointer | | |MOVEC |Move Control Register | | |MOVEM |Move Multiple | | |MOVEP |Move Peripheral | | |MOVEQ |Move Quick | | |MOVES |Move Alternate Address | | | |Space | | + | Dual Mode: 64 bit processing intructions eg. Muls.l d0,d1:d2 | The Destination Operand is in 64 bit format +--------------------------------------------------------------------------+ | Addressing Modes and Assembler Syntax +--------------------------------------------------------------------------+ |Address Modes Syntax +--------------------------------------------------------------------------+ 01. Data register direct Dn ------------------------------------------------------------ 02. Address register direct An ------------------------------------------------------------ 03. Address register indirect (An)+ with postincrement ------------------------------------------------------------ 04. Address register indirect -(An) with predecrement ------------------------------------------------------------ 05. Address register indirect (d16,An) with displacement ------------------------------------------------------------ 06. Address register indirect (d8,An,Xn) with index (8bit displacement) ------------------------------------------------------------ 07. Address register indirect (bd,An,Xn) with index (base displacement) ------------------------------------------------------------ 08. Memory indirect postindexed ([bd,An],Xn,od) ------------------------------------------------------------ 09. Memory indirect preindexed ([bd,An,Xn],od) ------------------------------------------------------------ 0a. Absolute short (xxx).W ------------------------------------------------------------ 0b. Absolute long (www).L ------------------------------------------------------------ 0c. Program counter indirect (d16,PC) with displacement ------------------------------------------------------------ 0d. Program counter indirect with (d8,PC,Xn) index (8-bit displacement) ------------------------------------------------------------ 0e. Program counter indirect with (bd,An,Xn) index (base displacement) ------------------------------------------------------------ 0f. PC memory indirect postindexed ([bd,PC],Xn,od) ------------------------------------------------------------ 10. PC memory indirect preindexed ([bd,PC,Xn],od) ------------------------------------------------------------ 11. Immediate # ------------------------------------------------------------ +--------------------------------------------------------------------------+ | Instruction Assembler Syntax +--------------------------------------------------------------------------+ Instructions are separated by asterix lines. **************************************************************************** Add Binary Coded Decimal w/extend NAME ABCD -- Add binary coded decimal SYNOPSIS ABCD Dy,Dx ABCD -(Ay),-(Ax) Size = Byte FUNCTION Adds the source operand to the destination operand along with the extend bit, result is stored in the destination location. The addition is performed using binary coded decimal arithmetic. The operands, which are packed BCD numbers, can be addressed in two different ways: 1. Data register to data register: The operands are contained in the data registers specified in the instruction. 2. Memory to memory: The operands are addressed with the predecremented addressing mode using the address registers specified in the instruction. This operation is a byte operation only. Normally the Z condition code bit is set via programming before the start of an operation. That allows successful tests for zero results upon completion of multiple-precision operations. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|---|---|---|---|---|-----------| | 1 | 1 | 0 | 0 | Rx | 1 | 0 | 0 | 0 | 0 |R/M| Ry | +---------------------------------------------------------------+ R/M = 0 -> data register R/M = 1 -> address register Rx: destination register Ry: source register RESULT X - Set the same as the carry bit. N - Undefined Z - Cleared if the result is non-zero. Unchanged otherwise. V - Undefined C - Set if a decimal carry was generated. Cleared otherwise. **************************************************************************** ADD integer NAME ADD -- Add integer SYNOPSIS ADD ,Dn ADD Dn, Size = Byte, Word, Long FUNCTION Source- and destination-operand are added using binary addition. The result is stored in the destination location The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination as well as the operand size. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 1 | REGISTER | OP-MODE | MODE | REGISTER | +---------------------------------------========================+ OP-MODE Byte Word Long ~~~~ ~~~~ ~~~~ 000 001 010 (Dn) + () -> Dn 100 101 110 () + (Dn) -> REGISTER One of the 8 datas registers If is source, allowed addressing modes are: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An * |001 |N reg. An| | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data |111 | 100 | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ * Word or Long only If is destination, allowed addressing modes are: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ When destination is an Address Register, ADDA instruction is used. RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. **************************************************************************** ADD Address NAME ADDA -- Add address SYNOPSIS ADDA ,An Size = Word, Long FUNCTION Adds the source operand to the destination address register, and stores the result in the destination address register. The size of the operation may be specified as word or long. The entire destination operand is used regardless of the operation size. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 1 | REGISTER | OP-MODE | MODE | REGISTER | +---------------------------------------========================+ P-MODE Indicates operation lenght: 011->one Word operation: source operand is extended to 32 bits 111->one Long operation REGISTER One of the 8 address registers. is always source, all addressing modes are allowed. +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An |001 |N reg. An| | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data |111 | 100 | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ RESULT None. **************************************************************************** ADD Immediate NAME ADDI -- Add immediate SYNOPSIS ADDI #, Size = Byte, Word, Long FUNCTION Adds the immediate data to the destination operand, and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size. FORMAT +---------------------------------------========================+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|-------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | SIZE | MODE | REGISTER | |---------------------------------------------------------------| | 16 BITS DATA (with last Byte) | 8 BITS DATA | |---------------------------------------------------------------| | 32 BITS DATA (included last Word) | +---------------------------------------------------------------+ SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the following: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. **************************************************************************** ADD 3-bit immediate Quick NAME ADDQ -- Add 3-bit immediate quick SYNOPSIS ADDQ #, Size = Byte, Word, Long FUNCTION Adds the immediate value of 1 to 8 to the operand at the destination location. The size of the operation may be specified as byte, word, or long. When adding to address registers, the condition codes are not altered, and the entire destination address register is used regardless of the operation size. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|-----------|-----------| | 0 | 1 | 0 | 1 | DATA | 0 | SIZE | MODE | REGISTER | +---------------------------------------========================+ DATA 000 ->represent value 8 001 to 111 ->immediate data from 1 to 7 SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the following: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An * |001 |N reg. An| | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ * Word or Long only. RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. **************************************************************************** ADD integer with eXtend NAME ADDX -- Add integer with extend SYNOPSIS ADDX Dy,Dx ADDX -(Ay),-(Ax) Size = Byte, Word, Long FUNCTION Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binary coded decimal arithmetic. The operands, which are packed BCD numbers, can be addressed in two different ways: 1. Data register to data register: The operands are contained in the data registers specified in the instruction. 2. Memory to memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction. The size of operation can be specified as byte, word, or long. Normally the Z condition code bit is set via programming before the start of an operation. That allows successful tests for zero results upon completion of multiple-precision operations. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|---|---|---|-----------| | 1 | 1 | 0 | 1 | Rx | 1 | SIZE | 0 | 0 |R/M| Ry | +---------------------------------------------------------------+ R/M = 0 -> data register R/M = 1 -> address register Rx: destination register Ry: source register SIZE 00->one Byte operation 01->one Word operation 10->one Long operation RESULT X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Cleared if the result is non-zero. Unchanged otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise. **************************************************************************** Logical AND NAME AND -- Logical AND SYNOPSIS AND ,Dn AND Dn, Size = Byte, Word, Long FUNCTION Performs a bit-wise AND operation with the source operand and the destination operand and stores the result in the destination. The size of the operation may be specified as byte, word, or long. The contents of an address register may not be used as an operand. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|-----------|-----------|-----------| | 1 | 1 | 0 | 0 | REGISTER | OP-MODE | MODE | REGISTER | +---------------------------------------========================+ OP-MODE Byte Word Long 000 001 010 (Dn)AND()-> Dn 100 101 110 ()AND(Dn)-> REGISTER One of the 8 datas registers If is source, allowed addressing modes are: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) |111 | 010 | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) |111 | 011 | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)|111 | 011 | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)|111 | 011 | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data |111 | 100 | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ If is destination, allowed addressing modes are: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ AND between two datas registers is allowed if you consider the syntax where Dn is at destination's place. If you use this instruction with an immediate data, it does the same as instruction ANDI. RESULT X - Not affected N - Set if the most-significant bit of the result was set. Cleared otherwise. Z - Set if the result was zero. Cleared otherwise. V - Always cleared. C - Always cleared. **************************************************************************** Logical AND Immediate NAME ANDI -- Logical AND immediate SYNOPSIS ANDI #, Size = Byte, Word, Long FUNCTION Performs a bit-wise AND operation with the immediate data and the destination operand and stores the result in the destination. The size of ther operation can be specified as byte, word, or long. The size of the immediate data matches the operation size. FORMAT +---------------------------------------========================+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|-------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | SIZE | MODE | REGISTER | |---------------------------------------------------------------| | 16 BITS DATA (with last Byte) | 8 BITS DATA | |---------------------------------------------------------------| | 32 BITS DATA (included last Word) | +---------------------------------------------------------------+ SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER is always destination, addressing modes are the following: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |N reg. Dn| | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ RESULT X - Not affected N - Set if the most-significant bit of the result was set. Cleared otherwise. Z - Set if the result was zero. Cleared otherwise. V - Always cleared. C - Always cleared. **************************************************************************** Logical AND Immediate to CCR NAME ANDI to CCR -- Logical AND immediate to condition code register SYNOPSIS ANDI #,CCR Size = Byte FUNCTION Performs a bit-wise AND operation with the immediate data and the lower byte of the status register. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | |---|---|---|---|---|---|---|---|-------------------------------| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 BITS IMMEDIATE DATA | +---------------------------------------------------------------+ RESULT X - Cleared if bit 4 of immed. operand is zero. Unchanged otherwise. N - Cleared if bit 3 of immed. operand is zero. Unchanged otherwise. Z - Cleared if bit 2 of immed. operand is zero. Unchanged otherwise. V - Cleared if bit 1 of immed. operand is zero. Unchanged otherwise. C - Cleared if bit 0 of immed. operand is zero. Unchanged otherwise. **************************************************************************** Logical AND Immediate to SR (privileged) NAME ANDI to SR -- Logical AND immediate to status register (privileged) SYNOPSIS ANDI #,SR Size = Word FUNCTION Performs a bit-wise AND operation with the immediate data and the status register. All implemented bits of the status register are affected. FORMAT +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | |---------------------------------------------------------------| | 16 BITS IMMEDIATE DATA | +---------------------------------------------------------------+ RESULT X - Cleared if bit 4 of immed. operand is zero. Unchanged otherwise. N - Cleared if bit 3 of immed. operand is zero. Unchanged otherwise. Z - Cleared if bit 2 of immed. operand is zero. Unchanged otherwise. V - Cleared if bit 1 of immed. operand is zero. Unchanged otherwise. C - Cleared if bit 0 of immed. operand is zero. Unchanged otherwise. **************************************************************************** Arithmetic Shift Left and Arithmetic Shift Right NAME ASL, ASR -- Arithmetic shift left and arithmetic shift right SYNOPSIS ASd Dx,Dy ASd #,Dy ASd where d is direction, L or R Size = Byte, Word, Long FUNCTION Performs an arithmetic shifting bit operation in the indicated direction, with an immediate data, or with a data register. If you shift address contents, you can only do ONE shift, and your operand is ONE word exclusively. ASL: <-- C <------ OPERAND <--- 0 | | X <---' ASR: --> .---> OPERAND ------> C | T | | | | `----' `---> X FORMAT In the case of the shifting of a register: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|-----------|---|-------|---|---|---|-----------| | 1 | 1 | 1 | 0 | NUMBER/ |dr | SIZE |i/r| 0 | 0 | REGISTER | | | | | | REGISTER | | | | | | | +---------------------------------------------------------------+ In the case of the shifting of a memory area: ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------+ |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|-----------|-----------| | 1 | 1 | 1 | 0 | 0 | 0 | 0 |dr | 1 | 1 | MODE | REGISTER | +---------------------------------------========================+ NUMBER/REGISTER Specifies number of shifting or number of register which contents the number of shifting. If i/r = 0, number of shifting is specified in the instruction as immediate data If i/r = 1, it's specified in the data register. If dr = 0, right shifting If dr = 1, left shifting SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER For a register shifting: Indicates the number of data register on which shifting is applied. For a memory shifting: indicates operand which should be shifted. Only addressing modes allowed are: +-------------------------------+ +-----------------------------+ |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn | - | - | | Abs.W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | Abs.L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |N reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |N reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |N reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |N reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |N reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |N reg. An| | #data | - | - | |-------------------------------| +-----------------------------+ |([bd,An,Xi]od) |110 |N reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |N reg. An| +-------------------------------+ RESULT X - Set according to the list bit shifted out of the operand. Unaffected for a shift count of zero. N - Set if the most-significant bit of the result is set. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if the most significant bit is changed at any time during the shift operation. Cleared otherwise. C - Set according to the list bit shifted out of the operand. Cleared for a shift count of zero. **************************************************************************** bingbangbong Conditional branch NAME Bcc -- Conditional branch SYNOPSIS Bcc