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Re: [MiNT] Super()
>> Anyways, when the stacked PC does not point to the right place,
>> instruction decoding and checking, what is the fault's cause, does
>> not seem possible to be done in software.
>>
>> Any ideas?
>
> The existing mmu_sigbus is not enough to determine the required
> informations?
To use Motorola's wording, it "may" be enough. Sometimes. And sometimes not.
> I think the fault address is much more interesting
> (and the type of the access, read or write) instead the PC.
You know, the stack provides information on the fault address, whether this
was read, write, or read-modify-write, and the size of the operation. Say we
could ignore writes (eventhough there is information what to write), but I
see some problem that remains with reads.
Say we have a read from the cookie jar pointer to the d0 register. I.e.
move.l $05a0.w,d0. This causes bus error, the stacked information is enough
to recognize that it is a read, it is from the address 0x05a0, and it is
long. But there is no information (at least: I can't see it) on where to
store the data to; i.e. the exception handler will not know that the data
should go to the register d0.
To know this, it must decode the instruction word. But the stacked PC "not
necessarily" points to the instruction word, so the handler can't decode it
reliably. And if it can't decode it, it can't emulate it either.
The question, that I don't know the answer to, is:
What exactly happens, if after mid-instruction bus fault, and when stacked
PC does not point to the offending instruction, the CPU is requested to
resume?
I guess that the problem may be solved with experiments, but perhaps someone
already knows that and can provide the information. As I see it currently,
Motorola manuals are not sufficient.
--
CVV
Konrad M.Kokoszkiewicz, http://draco.atari.org
** Ea natura multitudinis est,
** aut seruit humiliter, aut superbe dominatur.
** Taka to juz natura pospólstwa, albo sluzalczo sie plaszczy,
** albo bezczelnie sie panoszy. (Liwiusz XXIV, 25).