Say we have a read from the cookie jar pointer to the d0 register. I.e.
move.l $05a0.w,d0. This causes bus error, the stacked information is enough
to recognize that it is a read, it is from the address 0x05a0, and it is
long. But there is no information (at least: I can't see it) on where to
store the data to; i.e. the exception handler will not know that the data
should go to the register d0.
To know this, it must decode the instruction word. But the stacked PC "not
necessarily" points to the instruction word, so the handler can't decode it
reliably. And if it can't decode it, it can't emulate it either.
The question, that I don't know the answer to, is:
What exactly happens, if after mid-instruction bus fault, and when stacked
PC does not point to the offending instruction, the CPU is requested to
resume?