Re: [MiNT] Trans.: Re: Questions about 68040

[Petr Stehlik <joy@sophics.cz>]

V Čt, 08. 07. 2004 v 07:02, Xavier Joubert píše:
> This is impossible on 68 040 and 68 060 ! These CPUs cannot simulate a read or 
> write access. They always restart an access on an RTE. This is a major 
> differemnce between 68 030 and 68 0[46]0.

this is what I tried to warn about earlier but didn't remember the facts
:)

> When you encounter a bus fault for reading of 0x5a0, tweak PMMU to allow for 
> reading (and reading only) of 0x0-0x1000 (or 0x0-0x2000, I don't which page 
> size MiNT uses), modify SR on stack to set TRACE mode, and install tour own 
> trace handler. Then ReTurn from Exception.

Or if you don't let it read the address (say if it's a hardware reg) but
you want to supply your own value to the right register you basically
have to write a 68040 emulator.

Petr