[MiNT] Trans.: Re: Questions about 68040

[Xavier Joubert <xavier.joubert@free.fr>]

----- Message transféré de Xavier Joubert <xavier.joubert@free.fr> -----
   Date : Thu,  8 Jul 2004 06:56:19 +0200
     De : Xavier Joubert <xavier.joubert@free.fr>
Adresse de retour :Xavier Joubert <xavier.joubert@free.fr>
  Sujet : Re: [MiNT] Questions about 68040
      À : Konrad Kokoszkiewicz <draco@obta.uw.edu.pl>

Hi Konrad,


Selon Konrad Kokoszkiewicz <draco@obta.uw.edu.pl>:
> On 68030 this is easy, because the bus error stack frame provides a field
> named "data input buffer", which is to be updated and the processor loads
> this data into its viscera on RTE, and then processes further (e.g.
> transfers to d0) automagically.
> 
> How do I do the same on 68040?

I should have answered earlier but missed time...

This is impossible on 68 040 and 68 060 ! These CPUs cannot simulate a read or 
write access. They always restart an access on an RTE. This is a major 
differemnce between 68 030 and 68 0[46]0.

You have to find another way. Here is a suggestion :

When you encounter a bus fault for reading of 0x5a0, tweak PMMU to allow for 
reading (and reading only) of 0x0-0x1000 (or 0x0-0x2000, I don't which page 
size MiNT uses), modify SR on stack to set TRACE mode, and install tour own 
trace handler. Then ReTurn from Exception.

You may get another bus fault (if the program tries to copy 0x5a0 content to 
another place - you'll have to terminate the process in this case, I think), or 
a trace exception.

In the trace exception handler, restore PMMU state, turn off trace mode on the 
stack and restore original trace handler.

You may have to find a way to deny task switching during this time to ensure 
MiNT won't switch to another process before you restore the trace handler.


Hope this help,


Xavier
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