Re: [MiNT] Trans.: Re: Questions about 68040

["Konrad Kokoszkiewicz" <draco@obta.uw.edu.pl>]

> This is impossible on 68 040 and 68 060 ! These CPUs cannot simulate
> a read or write access. They always restart an access on an RTE. This
> is a major differemnce between 68 030 and 68 0[46]0.

So, the "full restart architecture" means that the CPU does not stack enough
information to resume the execution at any point, but retains a large
portion of the information in its internals, and thus its internal context
cannot be radically modified by stack frame modification. Do I understand
this well?

> When you encounter a bus fault for reading of 0x5a0, tweak PMMU to
> allow for reading (and reading only) of 0x0-0x1000 (or 0x0-0x2000, I
> don't which page size MiNT uses), modify SR on stack to set TRACE
> mode, and install tour own trace handler. Then ReTurn from Exception.
>
> You may get another bus fault (if the program tries to copy 0x5a0
> content to another place - you'll have to terminate the process in
> this case, I think), or a trace exception.
>
> In the trace exception handler, restore PMMU state, turn off trace
> mode on the stack and restore original trace handler.
>
> You may have to find a way to deny task switching during this time to
> ensure MiNT won't switch to another process before you restore the
> trace handler.

Hmm. Ok, but the 68040 manual states, that the trace exception occurs after
the instruction completion. So, this move.l 0x05a0,d0 will actually complete
before the trace exception occurs, i.e. the longword will be loaded to the
register. So, I presume, the trace exception in your proposal is solely for
restoring the state of the PMMU, right?

--
CVV
Konrad M.Kokoszkiewicz, http://draco.atari.org

** Ea natura multitudinis est,
** aut seruit humiliter, aut superbe dominatur.
** Taka to juz natura pospólstwa, albo sluzalczo sie plaszczy,
** albo bezczelnie sie panoszy. (Liwiusz XXIV, 25).