Re: [MiNT] Low-memory protection

[Xavier Joubert <xavier.joubert@free.fr>]

Hi,


Some thoughts for completeness...

I think we can say Milan is "Atari compatible" in that it can run well written
software designed for original Atari hardware. This missing feature is however
a problem for programmers. One can miss a minor bug on Milan that will crash
instantly on another hardware. This problem exists also on CT2 accelerator
board. CT60 was designed with this in mind.

040 and 060 only support 4 and 8 kb PMMU pages. 2 kb pages are not available.

This problem could be fixed by reprogramming the logic, given there's enough
space available... This could obviously slow the whole computer down. The real
problem here is that logic sources are not available, and even if they were, I
don't who have skills and time to work on this.

Selon Roger Burrows <anodyne@cyberus.ca>:
> For better compatibility, the bus error interrupt handler could be updated so
> that the user sees no error for accesses to locations 0x800->0x1fff.  This
> could be done by rerunning the failing instruction in supervisor mode.  If
> this
> is feasible, this ought to be a subsidiary run-time option, since it has the
> potential to be a performance killer.

This is feasible by :
- copying the faulty instruction in a reserved space followed by the code to
return to user mode and rts,
- putting the adress of the instruction folowing the faulty one on the user
stack (as the rts return adress)
- modifying the bus error stack so the system retry execution in our reserved
space in supervisor mode.

The problem with this is that it introduces a nice security hole. One can use
this to write any memory location in supervisor mode, by first writing the
desired value between 0x800 and 0x1fff, then moving this value from there to
the desired (supervisor only) address. This instruction will be executed in
supervisor mode...

And this is a performance killer, of course.


Best regards,


Xavier