Re: [MiNT] Low-memory protection

["Roger Burrows" <anodyne@cyberus.ca>]

On 26 Apr 2006 at 17:45, Odd Skancke wrote:

> > 
> > > Yes, but accesses to the first 2Kb of ram should not be controlled by
> > > the PMMU, but by the address logic.
> > 
> > Say which standard? Anyway the Milan hardware don't do this (and I don't 
> > think this can be marked as hardware bug as the hardware is designed in 
> > this way).
> 
>  The Atari hardware was designed this way, to protect the system
> variables/interrupt vectors, etc. Altho I cannot quote any documentation
> right now (anyone who can confirm what I state here?),

A) ST
See the Developer's Kit: "Engineering Hardware Specification of the Atari ST 
Computer System", page 25:

----- snip -----
8. Memory Map
The first 2 Kbyte of ST memory is reserved for the exception vector table and 
supervisor stack.  This area along with I/O space is protected for supervisor 
references only.  Accessing supervisor protected areas while in the user state 
will result in a bus error.  A 4 word portion of ROM is shadowed at the start 
of RAM for the reset stack pointer and program counter.  Writing to this area 
or any ROM location will also result in a bus error.
----- snip -----

Since the ST has no PMMU, the bus error *must* be provided by the address 
logic.


B) TT
In the Developer's Kit: "Atari TT030 Hardware Reference Manual", in section 
II.3 ROM, it states:

----- snip -----
An image of the first 8 bytes of ROM resides in the first 8 bytes of the ST 
compatible image.  These first 8 bytes (0x00000000-0x00000007, or 0xFF000000-
0xFF000007 in the image) are accessible *only* in supervisor mode.  Attempts to 
read from this area in user mode, or any write, results in a bus error.
----- snip -----

and in II.4 RAM, it states:

----- snip -----
The first 0x800 bytes (2K) of RAM (0x00000008-0x000007FF, or 0xFF000008-
0xFF0007FF in the image) are accessible only in supervisor mode.  Attempts to 
read or write to this area in user mode results in a bus error.
----- snip -----

I think that a system could be almost-compatible by using the PMMU with 2K 
pages, but strict compatibility (those first 8 bytes) requires address logic.  
But all this is pretty academic; what we have is Milans without the appropriate 
address logic, and with 8K PMMU pages.  It seems the best we can do is to 
protect the first 8K via the PMMU.  As Frank suggested, the kernel could update 
the primary MMU tree to make the first page supervisor only.  As Odd pointed 
out, there could be user-accessible data in the 2K-to-8K region, so this ought 
to be a MiNT run-time option.

For better compatibility, the bus error interrupt handler could be updated so 
that the user sees no error for accesses to locations 0x800->0x1fff.  This 
could be done by rerunning the failing instruction in supervisor mode.  If this 
is feasible, this ought to be a subsidiary run-time option, since it has the 
potential to be a performance killer.

Regards,
Roger Burrows