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[MiNT] [PATCH] Fix Ssystem(S_CTRLCACHE) in mintv4e.prg
Hello.
I noticed I clobbered by mistake a register in Ssystem(S_CTRLCACHE) in
mintv4e.prg. As a result, any program calling that system call (such as
MyAES) turned the cache into a random state.
ctrlcache.patch:
Fix Ssystem(S_CTRLCACHE) bug in mintv4e.prg. Contributed by Vincent Riviere.
Alan, please commit!
--
Vincent Rivière
diff -x CVS -aurN freemint.orig/sys/arch/cpu.S freemint/sys/arch/cpu.S
--- freemint.orig/sys/arch/cpu.S 2011-06-13 09:52:06.000000000 +0200
+++ freemint/sys/arch/cpu.S 2011-09-15 21:17:52.750000000 +0200
@@ -349,7 +349,11 @@
dc.w 0x0002,0x0010,0x0000,0x0000
dc.w 0x0040,0x0080,0x0000,0x0000
-l2c030: lea cacr30,a0
+l2c030:
+#ifdef __mcoldfire__
+ move.l d3,-(sp)
+#endif
+ lea cacr30,a0
clr.l d1
moveq #0x07,d2
l30:
@@ -360,8 +364,8 @@
#endif
bcc.s s30
#ifdef __mcoldfire__
- move.w (a0),d0
- or.l d0,d1
+ mvz.w (a0),d3
+ or.l d3,d1
#else
or.w (a0),d1
#endif
@@ -373,9 +377,16 @@
dbra.w d2,l30
#endif
move.l d1,d0
+#ifdef __mcoldfire__
+ move.l (sp)+,d3
+#endif
rts
-c2l030: lea ccw30,a0
+c2l030:
+#ifdef __mcoldfire__
+ move.l d3,-(sp)
+#endif
+ lea ccw30,a0
clr.l d1
moveq #0x0f,d2
c30:
@@ -386,8 +397,8 @@
#endif
bcc.s s31
#ifdef __mcoldfire__
- mvz.w (a0),d0
- or.l d0,d1
+ mvz.w (a0),d3
+ or.l d3,d1
#else
or.w (a0),d1
#endif
@@ -399,6 +410,9 @@
dbra.w d2,c30
#endif
move.l d1,d0
+#ifdef __mcoldfire__
+ move.l (sp)+,d3
+#endif
rts
// 68040, bit 15 enables the instruction cache, bit 31 enables the data cache.
@@ -485,7 +499,11 @@
eori.l #0x58006000,d0 // adjust reverted bits
rts
-c2l060: lea ccw60,a0
+c2l060:
+#ifdef __mcoldfire__
+ move.l d3,-(sp)
+#endif
+ lea ccw60,a0
lsr.l #0x08,d0 // first 13 bits of CACR aren't used
lsr.l #0x04,d0
clr.l d1
@@ -493,8 +511,8 @@
c60: lsr.l #0x01,d0
bcc.s s61
#ifdef __mcoldfire__
- mvz.w (a0),d0
- or.l d0,d1
+ mvz.w (a0),d3
+ or.l d3,d1
#else
or.w (a0),d1
#endif
@@ -511,6 +529,9 @@
#else
eor.w #0x4f00,d0 // adjust reverted bits
#endif
+#ifdef __mcoldfire__
+ move.l (sp)+,d3
+#endif
rts
#endif